The present invention relates to a semiconductor device and, more particularly, to a transistor in a semiconductor device and a method for fabricating the same.
As a semiconductor device becomes highly integrated, it has become increasingly important to fabricate a transistor capable of ensuring high current drivability while maintaining the margin of a channel length in a narrow area. In particular, it is essential for the fabrication of high speed products to ensure high current drivability.
According to the prior art, in order to ensure high current drivability, a method of scaling the thickness of a gate insulation layer has been employed. However, in a highly integrated semiconductor device, an equivalent oxide thickness (EOT) is less than 2 nm and thus current leakage occurs in the gate dielectric layer. Therefore, such a method has a limit in ensuring the high current drivability.
In order to overcome such a limitation, a technology capable of increasing the mobility of a carrier has been recently proposed. For example, U.S. Pat. No. 6,861,318 discloses a method for improving on-current by applying stress to a channel region formed below a gate to increase the mobility of a carrier. Hereinafter, the method will be described in more detail with reference to FIG. 1.
FIG. 1 illustrates a cross-sectional view of a method for fabricating a transistor in a semiconductor device according to the prior art. Referring to FIG. 1, a PMOS transistor will be described as one example.
As shown in FIG. 1, an isolation layer 11 is formed on a substrate 10 to isolate an active region of the substrate 10. In general, the substrate 10 includes silicon. Then, a gate 100 including a gate insulation layer 12, a gate electrode 13 and a gate hard mask 14 is formed on the substrate 10.
After an insulation layer for a gate spacer is formed on the resultant structure including the gate 100, the entire surface of the insulation layer is etched to form a gate spacer 15 on both sidewalls of the gate 100. After the substrate 10 is etched using the gate 100 and the gate spacer 15 as an etch barrier to form a recess 16 in source/drain regions of the substrate 10, an epitaxial SiGe layer 17 is formed to fill the recess 16.
In the case of fabricating the transistor in such a manner, stress is applied to a channel region 18 due to the difference between the lattice constant of the substrate 10 including silicon and the lattice constant of the epitaxial SiGe layer 17, so that the mobility of a carrier is increased. Since the epitaxial SiGe layer 17 has a lattice constant larger than that of the substrate 10, the compressive stress is applied to the channel region 18 to increase hole mobility. In particular, the lattice constant of the epitaxial SiGe layer 17 is further increased as the mole fraction of germanium contained in the epitaxial SiGe layer 17 is increased. However, the fabricating method of the transistor as described above has the following problems.
First, the stress applied to the channel region 18, due to the difference between the lattice constant of the substrate 10 and the lattice constant of the epitaxial SiGe layer 17, is rapidly reduced as the width of the gate spacer 15 is increased (reference document: K. Ota, et al, “Scalable eSiGe S/D Technology with less layout dependence for 45 nm, VLSI 2006”). That is, since the stress applied to the channel region 18 is changed according to the width of the gate spacer 15, properly adjusting the degree of on-current based on the mobility of the carrier is difficult.
Furthermore, in order to increase the stress applied to the channel region 18 to increase the mobility of the carrier, it is preferable to increase the difference between the lattice constant of the substrate 10 and the lattice constant of the epitaxial SiGe layer 17. To this end, the mole fraction of germanium contained in the epitaxial SiGe layer 17 should be increased. However, if the mole fraction of germanium contained in the epitaxial SiGe layer 17 is increased beyond a certain level (e.g., mole fraction 0.2), a defect such as dislocation may occur in the epitaxial SiGe layer 17. Such a defect may cause current leakage.